Key:
   $rd      Instr[15:11]
   $rs      Instr[25:21]
   $rt      Instr[20:16]
   Imm5     5-bit signed immediate
   Imm5u    5-bit unsigned immediate
   Imm16    16-bit signed immediate
   Imm16u   16-bit unsigned immediate

Selected Basic Integer Arithmetic Instructions
-------------------------------------------------------------------------------------------------------
add        $rd,$rs,$rt       Addition with overflow
                             GPR[rd] <-- GPR[rs] + GPR[rt]
addu       $rd,$rs,$rt       Addition "unsigned" without overflow
                             GPR[rd] <-- GPR[rs] + GPR[rt]
addi       $rt,$rs,Imm16     Addition immediate with overflow
                             GPR[rt] <-- GPR[rs] + Imm16
addiu      $rt,$rs,Imm16     Addition immediate "unsigned" without overflow
                             GPR[rt] <-- GPR[rs] + Imm16
div        $rs,$rt           Division with overflow
                             $lo <-- GPR[rs]/GPR[rt]
                             $hi <-- GPR[rs]%GPR[rt]
divu       $rs,$rt           Division "unsigned" without overflow
                             $lo <-- GPR[rs]/GPR[rt]
                             $hi <-- GPR[rs]%GPR[rt]
mul        $rd,$rs,$rt       Multiplication without overflow
                             GPR[rd] <-- (GPR[rs]*GPR[rt])[31:0]
mult       $rs,$rt           Multiplication without overflow
                             $hi <-- (GPR[rs]*GPR[rt])[63:32]
                             $lo <-- (GPR[rs]*GPR[rt])[31:0]
multu      $rs,$rt           Multipication "unsigned" without overflow
                             $hi <-- (GPR[rs]*GPR[rt])[63:32]
                             $lo <-- (GPR[rs]*GPR[rt])[31:0]
sub        $rd,$rs,$rt       Subtraction with overflow
                             GPR[rd] <-- GPR[rs] - GPR[rt]
subu       $rd,$rs,$rt       Subtraction unsigned without overflow
                             GPR[rd] <-- GPR[rs] - GPR[rt]
sra        $rd,$rt,Imm5u     Shift right arithmetic (with sign-extension)
                             GPR[rd] <-- GPR[rt] >> Imm5u
srav       $rd,$rt,$rs       Shift right arithmetic variable (with sign-extension)
                             GPR[rd] <-- GPR[rt] >> GPR[rs]


Selected Basic Logic Instructions
-------------------------------------------------------------------------------------------------------
and        $rd,$rs,$rt       Bitwise AND
                             GPR[rd[i]] <-- GPR[rs[i]] & GPR[rt[i]], i = 0..31
andi       $1,$2,Imm16u      Bitwise AND immediate (immediate is zero-extended)
                             GPR[rd[i]] <-- GPR[rs[i]] & $Imm16u[i], i = 0..31
nor        $1,$2,$3          Bitwise NOR
                             GPR[rd[i]] <-- !(GPR[rs[i]] | GPR[rt[i]]), i = 0..31
or         $1,$2,$3          Bitwise OR
                             GPR[rd[i]] <-- GPR[rs[i]] | GPR[rt[i]], i = 0..31
ori        $1,$2,100         Bitwise OR immediate (immediate is zero-extended)
                             GPR[rd[i]] <-- GPR[rs[i]] | $Imm16u[i], i = 0..31
xor        $1,$2,$3          Bitwise XOR (exclusive OR)
                             GPR[rd[i]] <-- GPR[rs[i]] ^ GPR[rt[i]], i = 0..31
xori       $1,$2,100         Bitwise XOR immediate (immediate is zero-extended)
                             GPR[rd[i]] <-- GPR[rs[i]] ^ $Imm16u[i], i = 0..31
sll        $rd,$rt,Imm5u     Shift left logical
                             GPR[$rd] <-- GPR[$rt] << Imm5u
sllv       $rd,$rt,$rs       Shift left logical variable
                             GPR[rd] <-- GPR[rt] << GPR[rs]
srl        $rd,$rt,Imm5u     Shift right logical (no sign-extension)
                             GPR[rd] <-- GPR[rt] >> Imm5u
srlv       $rd,$rt,$rs       Shift right logical variable (no sign-extension)
                             GPR[rd] <-- GPR[rt] >> GPR[rs]
slt        $rd,$rs,$rt       Set less than
                             GPR[rd] <-- (GPR[rs] < GPR[rt])
slti       $rd,$rs,Imm16     Set less than immediate


Selected Basic Control-of-flow Instructions
-------------------------------------------------------------------------------------------------------
beq        $rs,$rt,label     Branch if equal
                             if ( GPR[rs] == GPR[rt] ) PC <-- PC + (label << 2)*
bne        $rs,$rt,label     Branch if not equal
                             if ( GPR[rs] != GPR[rt] ) PC <-- PC + (label << 2)*
bgtz       $rs,label         Branch if greater than zero
                             if ( GPR[rs] > 0 ) PC <-- PC + (label << 2)*
bltz       $rs,label         Branch if less than zero
                             if ( GPR[rs] < 0 ) PC <-- PC + (label << 2)*
bgez       $rs,label         Branch if greater than or equal to zero
                             if ( GPR[rs] >= 0 ) PC <-- PC + (label << 2)*
blez       $rs,label         Branch if less than or equal to zero
                             if ( GPR[rs] <= 0 ) PC <-- PC + (label << 2)*
break                        Break execution
                             Signal an exception
j          target            Jump unconditionally
                             PC <-- (target << 2)*
jal        target            Jump and link (puts return address in $ra)
                             GPR[ra] <-- PC + 4*
                             PC <-- (target << 2)*
jalr       $rs               Jump and link register (puts return address in $ra)
                             GPR[ra] <-- PC + 4*
                             PC <-- GPR[rs]
jalr       $rd,$rs           Jump and link register (puts return address in first operand)
                             GPR[rd] <-- PC + 4*
                             PC <-- GPR[rs]
jr         $rs               Jump register unconditionally
                             PC <-- GPR[rs]

* More or less... see notes or MIPS reference for details.

Basic Data Transfer Instructions
-------------------------------------------------------------------------------------------------------
lb         $rt,offset(rs)    Load byte
                             GPR[rt] <-- SignExtend(Mem[GPR[rs] + offset]0:7)
lh         $rt,offset(rs)    Load halfword
                             GPR[rt] <-- SignExtend(Mem[GPR[rs] + offset]0:15)
lw         $rt,offset(rs)    Load word
                             GPR[rt] <-- Mem[GPR[rs] + offset]
sb         $rt,offset(rs)    Store byte
                             Mem[GPR[rs] + offset] <-- GPR[rt]0:7
sh         $rt,offset(rs)    Store halfword
                             Mem[GPR[rs] + offset] <-- GPR[rt]0:15
sw         $rt,offset(rs)    Store word
                             Mem[GPR[rs] + offset] <-- GPR[rt]


Miscellaneous Basic Instructions
-------------------------------------------------------------------------------------------------------
syscall                      Issue a system call specified by $v0


Basic Exception-related Instructions
-------------------------------------------------------------------------------------------------------
teq        $rs,$rt           Trap if register contents are equal
                             If GPR[rs] == GPR[rt] then Trap
tge        $1,$2             Trap if first register contents greater or equal
                             If GPR[rs] >= GPR[rt] then Trap