Solution for CS 2506 Spring 2016 MIPS01 ------------------------------------------------------------------------------- 1. Suppose that, due to a manufacturing defect, the RegDst control signal suffers a stuck-at-0 error. That is, the RegDst signal is always set to 0 regardless of circumstances. Assume that the rest of the hardware operates as designed. a) [12 points] Would any of the supported instructions still always execute correctly? If so, which one(s) and why? Answer: It should be obvious that any instruction that requires RegDst to be set to 0 or don't care(X) would be unaffected. That would include: lw, sw, beq, j All R-type instructions (add, sub, and, or, slt) would be affected, since they use Instruction[15:11] to specify the Write register b) [12 points] Would any of the other supported instructions possibly execute correctly (i.e., produce all the logically correct results and not produce any unintended side effects)? If so, which one(s) and why? Answer: If the second source register (Instruction[20:16]) and the destination register (Instruction[15:11]) happen to be the same, then R-type instructions would execute correctly. e.g., $t1 = $t2 + $t1 2. Suppose that, due to a manufacturing defect, the RegWrite control signal suffers a stuck-at-1 error. That is, the RegWrite line is always set to 1 regardless of circumstances. Assume that the rest of the hardware operates as designed. a) [12 points] Would any of the supported instructions still always execute correctly? If so, which one(s) and why? Answer: It should be obvious that any instruction that requires RegWrite to be set to 1 would be unaffected. That would include R-format instructions and load instruction: add, sub, and, or, slt, lw sw, beq, j instructions would be affected, as they are not supposed to update a register. b) [12 points] Would any of the other supported instructions possibly execute correctly (i.e., produce all the logically correct results and not produce any unintended side effects)? If so, which one(s) and why? Answer: Nope. sw, beq, j instructions should not write a value to a register. (Heads-up) One might argue that a write to a register might not have a side effect. e.g., a write to a $zero register will be ignored; a write could be silent (old value and new value could be same); etc. 3. [10 points] The above single-cycle datapath (SCD) includes two Shift left 2 units: one for beq instruction, another for j instruction. An alternative design could have a single Shift left 2 unit and use a MUX to choose an input to the shifter. Discuss why this alternative design is less efficient than the original design with two Shift left 2 units. Answer: Fixed-amount shifts can be easily implemented in hardware via wiring, but the 2x1 multiplexer requires multiple logic gates (2 AND, 1 OR, and 1 NOT), leading to hardware/performance cost. 4. A few easy ones about the SCD. Just state your conclusion; explanations will not be considered. a) [6 points] Among the supported I-type instructions, which instruction requires the ALUSrc control signal to be set to 0? Answer: beq beq compares 2 registers and takes a branch if they match b) [6 points] The MUX to the right of the Data memory unit input to the register file is necessary because of a difference between the R-format machine instructions and what other (single) supported machine instruction? Answer: lw lw is the only instruction that reads a value from the data memory and writes it to the register. c) [6 points] For the slt $t0, $t1, $t2 instruction in an assembly format, what should be the value of ALU result (an output of the ALU unit) if $t1 is 1 and $t2 is 2. Answer: 1 For slt, R[rd] = (R[rs]