Solution for CS 2506 Spring 2020 MIPS01 ------------------------------------------------------------------------------- 1. [15 points] Are the Branch and Zero signals both logically necessary? Or could one be omitted? Explain clearly. Answer: Both are necessary. Executing beq correctly requires that the branch be taken if an only if the current instruction is beq, AND if the ALU computes 0 when comparing the values stored in the relevant registers. So, Zero is logically necessary. And, the ALU may compute 0 (and therefore set Zero to 1) when the current instruction is NOT a beq. In that case, we do not want a branch to occur, so the Branch signal is also logically necessary. 2. [15 points] For which of the supported instructions does it not matter how the control signal Jump is set? Justify your answer precisely and completely. Answer: The setting of the Jump signal matters for every instruction. Jump controls the final MUX used to determine what address will be sent to the PC register. If the current instruction is NOT j, this MUX must send the output from the preceding MUX to PC; otherwise, the address sent to PC would be meaningless, since it would be formed from bits that were not even representing a jump distance. Therefore, for all non-j instructions, it is critical that Jump == 0. If the current instruction is j, then it is critical that the same MUX send the address computed from the immediate field of the j instruction to the PC (so the jump will be taken). Therefore, for a j instruction, it is critical that Jump == 1. 3. [20 points] Suppose that, due to a manufacturing error, the control line ALUSrc is always set to 0. Describe the circumstances, if any, under which the following instruction would still produce the intended result: lw $t3, 8($s7) # GPR[$t3] <-- Mem[GPR[$s7] + 8] Answer: First of all, this instruction SHOULD write the value stored at the address $s7 + 0 into the register $t3; that is $t3 should get Mem[$s7 + 8]. If ALUSrc == 0, the ALU will receive the value from Read data 2 as its right operand. For the lw instruction that will be the value read from the register $t3 (which is supposed to be written to). So, the ALU will compute the value $s7 + $t3, and send that to the Data memory unit as the address to be read from. Assuming that the process is allowed to read from that address, the value from Mem[$s7 + $t3] will be read from Data memory, and sent to the Register file to be written into the register $t3. So, the correct result will occur if and only if the following conditions are both true: 1: the process is allowed to read Mem[$s7 + $t3] 2: Mem[$s7 + $t3] == Mem[$s7 + 8] OR if 3: $t3 == 8 initially 4. See the assignment statement for the complete question, with diagrams. a) [10 points] Explain the circumstances under which Shift will be set to 0, and when Shift will be set to 1 Answer: Given the description of the way the MUX select bits must be set, Shift must be 1 if and only if the current instruction is sll. From the hardware perspective: Shift == 1 if opcode == 000000 and funct == 000000 Shift == 0 if opcode != 000000 or funct != 000000 b) [10 points] Explain why the Control unit cannot be used to set Shift. Answer: Setting Shift correctly requires examining the funct bits from the instruction, but the Control unit only receives the opcode bits. c) [10 points] What hardware unit can be used to set Shift? An existing one, or do we need a new one? If existing, explain. If a new one, explain what information it will need in order to operate correctly. Answer: Determining how to set Shift depends on knowing two facts: - is the current instruction R-type? - if so, does the funct field correspond to sll? Answering the first question seems to demand having the opcode bits, which are sent only to the Control unit; however, the Control unit already has the capability to tell the ALU control unit whether the current instruction is R-type. Therefore, the existing ALU control unit can set Shift correctly. 5. This question relates to the tradeoffs that were inherent in the design of the MIPS32 machine language, due to the decision to strictly adopt a 32-bit format for all machine instructions. The MIPS32 designers decided to use a 6-bit field for the opcode. That limited the number of different opcode values; as a direct result of this, the MIPS32 designers were forced to make some opcodes "special". For example, the opcode 000000 was used to specify R-format instructions, which then used a different set of bits (the funct field) to specify the actual instruction that was to be performed. And, a direct result of that was that the MIPS32 datapath needed a second control unit to handle decoding R-format instructions. Suppose the MIPS32 designers had decided to use 8 bits to specify the opcode for each instruction. a) [4 points] Easy question… how many different machine instructions could have been specified using this wider opcode field? Explain why. Answer: With an 8-bit opcode field, we could specify 2^8 or 256 different machine instructions. Now, the MIPS32 designers would still have chosen to use a 16-bit immediate field, and still have chosen to represent every machine instruction with 32 bits. b) [8 points] Describe how his would change the way I-format instructions would be formatted. Answer: If we have an 8-bit opcode field and a 16-bit immediate field, then an I-format instruction can only use 8 bits to specify the numbers for two registers. Therefore, register numbers are limited to 4 bits. c) [8 points] Describe any resulting changes that would have to be made to the version of the MIPS32 datapath hardware shown in Figure 1 to accommodate the new I-format design. Answer: With 4-bit register numbers, the datapath can only have 2^4 general registers, rather than 32.